This invention relates generally to clock generation, and more particularly to providing open-loop quadrature clock generation.
To address the ever-increasing need to increase the speed of computers and electronic appliances to process ever increasing amounts of data, designers have increased the clock frequency of computers and/or utilized parallel processing. Many electrical and computer applications and components have critical timing requirements that require clock waveforms that are precisely synchronized with a reference clock waveform.
One type of clock generator is a ring oscillator. Ring oscillators are widely used in electronic equipment such as computers, televisions, video-processing equipment and the like. Generally, a ring oscillator includes a single loop circuit that has an odd number of inverters. As the output signal is fed back into the inputs of the single direction loop, the output signal is inverted, resulting in a signal that varies between a high and a low signal. This creates a periodic signal with a well-defined and stable cycle.
Conventional main memory chips (e.g., a DDR II memory device) typically include a delay locked loop (DLL) to synchronize data timing to an external clock edge such as from a differential clock. As the data rate of memory devices increases, an exemplary clock may include a frequency multiplier within the memory devices, enabling data to be transferred at a rate of four (quad data rate, “QDR”) or more bits per clock cycle. One way to provide such a frequency multiplier is to utilize a quadrature phase generating DLL that is more complicated than a conventional DLL, and therefore consumes more power to minimize jitter and ensure fast exit time (the time delay between exiting a low power state and normal device operation). Another manner of providing a frequency multiplier is to utilize a phase locked loop (PLL). However, PLLs have been known to suffer from jitter accumulation due to their loop architecture and to self-generate a frequency as well as a phase. In addition, the lock-in time of a PLL can be as much as ten times longer than a DLL. The PLL lock-in time is generally not compatible with memory circuit/chip requirements such as low standby power consumption and fast exit/availability time.
Therefore, it would be desirable to be able to generate quadrature (or octal, etc.) clock phases from differential (two phase) clocks in a manner that provides for a low level of jitter while consuming a relatively small amount of power.